This is a  draft of my first thesis topic.  This thesis was never completed.  


A High-Speed Architecture for Decision Feedback Equalization
 

Abstract

A VLSI chip implementing a high-speed Decision Feedback Equalizer has been designed and laid out. It is an all-digital, static CMOS design, implemented in an 0.8 um, 3-layer metal process. Its main features are ten 8-bit by 7-bit 2's complement multipliers, thirteen simplified-architecture multiplier/adders, and a clock rate of exceeding 100 MHz. The specifics of the design are intended to permit the testing of a modified form of Decision Feedback Equalization called Multi-level Decision Feedback Equalization that has been proposed for use in an improved data detector for disk drives.

Chapter 1- Introduction
1.1 Inter-Symbol Interference

In digital communications channels where the response of the channel to a symbol to be transmitted is much longer than the symbol itself, a common source of signal distortion is inter-symbol interference (ISI). This means that the responses of the transmitted symbols overlap each other in time. The resulting superposition of signals causes shifts in the location of signal peaks and variances in signal amplitude. When signal distortion is too large, erroneous detections are made at the output. Therefore, as transmission rates increase, symbols are packed more closely together, increasing ISI and the likelihood of erroneous detections. But if the effects of ISI can somehow be reduced, the achievable transmission rate for a given error probability can be increased.

1.2 Decision Feedback Equalization

Decision Feedback Equalization (DFE) [1] is a technique used to eliminate all ISI so that the output consists only of the impulse response, d(k), plus some noise component. Consider the discrete-time model of a digital communication channel incorporating DFE shown in figure 1. In this channel, a digital data stream, ak, consisting of positive and negative impulses, enters the channel response block. The channel response block includes the response of the transmission media, plus that of filters that are used to shape the signal before and after its transmission. White noise is then factored in with the addition of the nk term. After sampling, the transformed signal, sk, enters the DFE through a linear transversal filter -- the forward FIR filter with coefficients wk. This filter is of sufficient length to delay the response to make it causal. It is designed to remove pre-cursor ISI from the response -- the ISI due to future symbols.

Figure 1: Digital Communication Channel with DFE
Next, the output of the forward filter, rk, is summed with the output of the feedback section. The bk coefficients of the feedback section, or backward filter, are chosen to match the combined response of the channel block and the forward filter to a unit impulse. That is, a copy of the system impulse response resides in the backward filter, so that when a vector of past decisions is convoluted with the coefficients of the backward filter, a good estimate of the post-cursor ISI -- the ISI due to past symbols -- is generated. When the output of the backward filter is subtracted from rk, all of the channel response except for the unit impulse response of a single ak input is removed.

The result of the summation, qk, is input into a decision rule that is in the form of a slicer. Assuming that past decisions have been correct, qk = ak + nk. The slicer simply takes the most significant bit of qk, the sign-bit, and outputs it as the estimated  decision value, +1 or -1. The ís then propagate through the backward filter. In equation form, the DFE is:

Coefficients used in equalization filters are typically calculated by adaptive update algorithms. The least mean-square (LMS), stochastic gradient algorithm [2] is the most commonly used, and was utilized for this design. The difference between the actual output, , and the desired output, , is the error signal, (), that drives this algorithm. For DFE the desired output is . The vector of coefficients for the forward equalizer, , is updated with the equation:

where sets the speed of adaptation and Sk is a vector of input symbols.

For the backward equalizer, the vector of coefficients, , is similarly calculated with the equation:

where sets the speed of adaptation and is a vector of detected symbols.

1.3 Multi-level Decision Feedback Equalization

Moon [3] proposed a modified version of DFE called Fixed-Delay Tree Search with Decision Feedback (FDTS/DF) for use in a disk drive data detector. Instead of equalizing the system response to a single unit impulse, this technique retains the first and largest value of intersymbol interference in addition to the impulse response to obtain a multi-level output. By retaining this extra signal energy, a higher signal-to-noise ratio (SNR) is achieved than with DFE, yielding a lower error rate. The changed equalization target, d(k) + b1d(k), is achieved by removing the first coefficient, b1, from the backward filter so that its coefficient vector becomes . The multi-level output (= ak+1 + b1ak + nk ) is then decoded into the proper sequence of bits by a fixed-length, exhaustive search tree detector. The predicted output from each of the four possible branches (tree depth=2), as show in figure 2, is compared with the actual output, the closest being chosen as the correct one. From the sequence required to generate this branch, the current symbol value, = {+1, -1}, is deduced. This is fed into a decision feedback loop, whose result will be summed with the output of the forward filter, as in DFE.

Figure 2: Tree of depth 2 with (d=1) minimum run-length violation
An analysis of FDTS/DF by Kenney [4] revealed that for the case of (d = 1) run length limited (RLL) coding schemes, which are often used in disk drives, certain simplifications can be applied to the decision tree. Branch 3 of figure 2 is not permitted under (d=1) RLL coding. Using linear discriminants to decide between the remaining three branches, two of the three linear discriminants required are equivalent and can be treated as one discriminant. These are the discrimants that decide between sequences 1 and 3 and sequences 2 and 4. The third linear discriminant, which decides between sequences 1 and 4, can be neglected due to the extremely low probability of its use. (The probability of an erroneous decision from eliminating this linear discriminant is some twenty orders of magnitude below the overall error rate for disk drives using the high data densities under consideration.)

By taking the one remaining linear discriminant of the decision tree and placing it in both the forward and backward filter loops, as shown in figure 3, the need for a separate tree search component is eliminated. This linear discriminant, which divides the decision space between = +1 and = -1, is (b1 + D), where D is the unit delay operator. Thus, the target response of FDTS/DF is multiplied by (b1 + D), yielding:

This simplified version of FDTS/DF is called Multi-Level Decision Feedback Equalization (MDFE) because it is architecturally identical to DFE. The only difference is that the algorithm for determining the coefficients of the forward and backward equalizers is changed so that the output becomes multi-level.

Figure 3: Block diagram of MDFE
The coefficients for use in MDFE are determined in mostly the same way as in DFE. One significant difference is the changed error signal, (), due to the changed target, , and actual, , outputs used in MDFE. Also, the b1 term is removed from its normal position in the backward filter and now is calculated by a separate algorithm for its use in the linear discriminant. Its update equation is:

whereis the rate of adaptation for .

Because the changed error signal, , now uses a future detected symbol, , a delay must be added to the coefficient update equations for the forward and backward equalizers. The update equation for the forward equalizer coefficients, , becomes:

And the update equation for the backward equalizer coefficients, , becomes:

Once the values for b1, and  are calculated,  and  must be multiplied through by the linear discriminant, (b1 + D), to obtain the actual coefficients to be loaded into the equalizers.

The DFE of this thesis was designed to satisfy the performance requirements of MDFE applied to disk drive data detection. It is hoped that this chip can be used to verify simulated results that predict that MDFE provides superior performance to the other disk data detection methods of peak detection and Partial Response (PR) Equalization while offering a simple, low-cost, low-power implementation. Figure 4 illustrates the predicted performance of MDFE on high-density magnetic recording channels. Note that the signal-to-noise ratio (SNR) of MDFE (which corresponds to the error rate) is clearly superior to the other methods at higher bit densities. Thus, MDFE holds the promise of significantly increasing disk drive storage density.
 
 

Figure 4: Comparison of error rates of MDFE with other detectors
 

 

Chapter 2 - Architecture
DFE System Overview

Simulations to determine Bandwidth

Hardware Models

Booth/Wooley

Fast Static SCMOS adders

Hardware Implementation

Layouts, Simulation Results:Propagation Delay

FF

Fast Adders

Multiplier

Backward Adder

Slicer

Global Routing and Clocks

Overall Chip: Area, Power, Speed, Transistor Count

Hardware Results

Future Work

 

 

BIBLIOGRAPHY
 



 

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